1. Field of the Invention
The present invention relates in general to the fabrication of semiconductor devices. More particularly, it relates to a self-aligned contact process which can provide a large process window for stable high yield in mass production.
2. Description of the Related Arts
Self-alignment is a technique in which multiple levels of regions on the wafer are formed using a single mask, thereby eliminating the alignment tolerance required by additional masks. This powerful approach is being used more often as circuit sizes decrease. Self-aligned contacts are often used in memory cells where contacts are limited only by the spacers and field oxide bird's beak or a contact window landing pad. Therefore, the mask contact window can be oversized relative to the contact area underneath, and no contact borders are needed, resulting in significant space saving. Referring to FIGS. 1A-1C, a conventional process of forming a self-aligned contact hole is illustrated in cross-sectional views. The process will be described as follows.
FIG. 1A shows a semiconductor substrate 10 having two closely spaced field effect transistors with gate electrodes 14, source/drain diffusion regions 18, and gate oxides 12. The gate electrodes 14, commonly consisting of polysilicon and silicide, are capped with an insulator 16 of silicon nitride. Next, a nitride or oxide layer is formed over the substrate surface using low pressure chemical vapor deposition (LPCVD), which is then anisotropically etched to form sidewall spacers 22 on the sidewalls of the gate electrodes 14 and the cap layers 16.
Referring to FIG. 1B, a conformal layer of etch barrier material 24 is deposited over the diffusion region 18, the cap layers 16, and the sidewall spacers 22. The barrier layer 24, which may also be called the liner layer, typically consists of silicon nitride. A layer of insulator 26 is deposited over the substrate as inter-layer dielectric (ILD) and is preferably planarized. The insulating layer 26 may consist of one or more dielectric depositions of spin on glass (SOG), silicon oxide, borophosphosilicate (BPSG), and so on.
Referring to FIG. 1C, using a photoresist mask 28, a contact hole can be etched in the insulating layer 26 with the liner layer 24 serving as an etch stop, which will be finally removed to expose the diffusion region 18. The etching of the insulating layer 26 is selective to the capping layers 16 and sidewall spacers 22 encapsulating the gate electrodes 14 so that the contact hole is self-aligning in nature.
However, as the semiconductor fabricating technology moves into deep sub-micron, it is increasingly recognized that the present technology for making self-aligned contact may be inadequate. The process window is not large enough for providing stable high yield in mass production.
Even though the process window can be improved by increasing the etch selectivity, the highest selectivity of oxide to nitride is only about 30-40 with the current dry etch technology, and the higher the selectivity, the more tapered the contact sidewall profile, as depicted by dotted lines 30 in FIG. 3C. Such a tapered profile causes a significant decrease in the contact area to the substrate, and consequently, increasing the contact resistance.
In consequence, it would be a significant improvement in the state of the art if the process window could be improved by a higher etch selectivity while increasing the contact area simultaneously.